1. Field of the Invention
The present invention relates to a process for fabricating a floating gate of a flash memory in a self-aligned manner, and more particularly to a process for fabricating a floating gate of a flash memory in a self-aligned manner using a polysilicon spacer as a buffer layer. Thus, current leakage caused by insufficient overlay between floating gate and STI can be prevented.
2. Description of the Prior Art
Flash memory is a type of erasable programmable read-only memory (EPROM), which in turn is a type of non-volatile memory. In general, flash memory includes two gates. One of the gates, known as a floating gate, is used for charge storage. The second gate, known as a control gate, is used for controlling the input and output of data. The floating gate is located beneath the control gate, and is generally in a floating state because there is no connection with external circuits. The control gate is normally wired to the word line. One of the advantages of flash memory is its capacity for block-by-block memory erasure. Furthermore, the speed of memory erasure is fast, and normally takes just 1 to 2 seconds for the complete removal of a whole block of memory. Therefore, in recent years, flash memory has been widely utilized in electrical consumer products, such as digital cameras, digital video cameras, cellular phones, laptop computers, mobile cassette players, and personal digital assistants (PDA).
The conventional process for fabricating flash memory usually uses photomasks to define the devices. Since the precision of the photomasks is limited, misalignment usually occurs for devices with a smaller line width. This causes open circuits or short circuits, and the electrical properties of the flash memory fail. Therefore, the device size of the conventional flash memory is limited by the design rule, so it is difficult to shrink the device size.
An object of the present invention is to solve the above-mentioned problems and provide a process for fabricating a floating gate of a flash memory in a self-aligned manner, which decreases tolerance and shrinks the device size.
Another object of the present invention is to provide a process for fabricating a floating gate of a flash memory to prevent current leakage caused by insufficient overlay between floating gate and STI.
To achieve the above objects, the process for fabricating a floating gate of a flash memory includes forming an isolation region in a semiconductor substrate, having a height higher than the semiconductor substrate; forming a gate oxide layer on the semiconductor substrate; forming a first polysilicon layer on the semiconductor substrate according to the contour of the isolation region to form a recess in the first polysilicon layer; filling a sacrificial insulator into the recess; selectively removing the first polysilicon layer in a self-aligned manner using the sacrificial insulator as a hard mask to expose the isolation region; forming a polysilicon spacer on the sidewalls of the first polysilicon layer; forming a first mask layer on the isolation region; removing the sacrificial insulator in the recess; defining a floating gate region; oxidizing the surfaces of the first polysilicon layer and polysilicon spacer in the floating gate region to form a polysilicon oxide layer; and using the polysilicon oxide layer as a mask to pattern the underlying first polysilicon layer and polysilicon spacer in a self-aligned manner to form a floating gate.
The present invention uses two self-alignment processes to form a floating gate. The first process involves using the height difference between the isolation region and the substrate to form a sacrificial insulator in a first polysilicon layer. Then, the first polysilicon layer is selectively removed using the sacrificial insulator as a hard mask in a self-aligned manner to expose the isolation region. The second process involves oxidizing the surfaces of the first polysilicon layer and polysilicon spacer in a floating gate region to form a polysilicon oxide layer. Then, the first polysilicon layer and polysilicon spacer are patterned using the polysilicon oxide layer as a mask in a self-aligned manner to form a floating gate. Since the floating gate is formed in a self-aligned manner, the device size can be shrunk.
Moreover, during the oxidation process to form a polysilicon oxide layer, the polysilicon spacer of the present invention serves as a buffer layer, which is oxidized and protects the floating gate from being oxidized. Thus, the floating gate and STI overlay, and current leakage caused by insufficient overlay can be prevented.